Structures which are increasingly common during the formation of a semiconductor device are conductor-filled vias formed through a semiconductor wafer. The vias provide passageways through the semiconductor wafer, for example from the front (circuit or active) side of the wafer to the back side of the wafer. The conductors may pass power or ground connections, or digital or analog signals from the front of the wafer to the back. These vias may be used with multichip modules to pass connections or signals between stacked semiconductor dice, or to connect a node such as a ground node formed on the front of a single die to the back of the die, which is then connected to a lead frame or other chip carrier.
Power and ground connections typically require a conductor having a larger diameter than is required for transmission of digital or analog signals due to higher current loads needed for power and ground connections than for signals. To conserve space on the surface of a semiconductor die, it is desirable to form digital and analog signal vias at a smaller size than power and ground connection vias. However, this approach requires additional processing, as the first type of via must be formed and filled before forming and filling the second type of via. Additional manufacturing complexity is required to fill the vias with different types of materials, for example copper within signal vias and a tin-lead alloy within power and ground connection vias.
A method which enables the simultaneous formation of different sized vias with different metallization, and structures resulting from the method, would be desirable.